Data Acquistion for the Source Test
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Setting up the FEE:
1) Load the FEE emulator FPGA (using Max+II) with the file 
emulator_top_stand_alone.sof
(NOTE: red edge of cable faces outward.)

2) Check the FEE switches:
Switch 5 up (all others down) for the counter mode.
All switches down for the walking-ones mode.
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Setting up the HTR:
1)Load the HTR FPGA (using Max+II) with the file 
htr_v05.sof

2) Check the clock-phase switch,
down-up-down-down

3) Turn the rotary switch on the front panel completely 
counter-clockwise (position 0)for the source mode.
Turn it to position 2 to select the stream mode 
(used for walking-ones test).

4) Make sure the 4th red light (and 5th if using two channels)
from the top on the front panel is off. 
If necessary, unplug and replug optical cable.

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Collecting data:
You will need to open two terminals on cmssun3, one for
executing step 2 below and one for step 3.

1) Go to the run directory,
cd /home/rohlf/run

2) Ready the CPU  for DMA running,
./source_read_v4

3) Start the DCC transmission (with a few seconds of step 2),
./dcc_control -t 1000 init run 
(where the number indicates the size of the run in milliseconds)

4) The data is written in the file dump.dat, view with
od -Ax -t x4 dump.dat | more
If using the FEE, check counter mode (source) with, 
./scan_new -s -f dump.dat
and walking-ones mode (steam) with,
./scan_new -w -f dump.dat

5) Rename the data file if you want to save it!